In recent years, in accordance with development of a process technology, a semiconductor device has been made more highly integrated, and a system LSI such as an SoC (system on a chip) on which a number of modules are mounted on one semiconductor device has been in widespread use. In such a semiconductor device, various kinds of operation performance are tested in an inspection step performed in a last stage of a manufacturing process. Only a good item which passes the test is shipped as a product.
When an operation performance test is performed, a low-level (or high-level) fixed signal is input to each module as a test mode signal. Further, when normal operation is performed, a fixed signal having an opposite phase to a phase upon test is input as the test mode signal. That is, in the case where the test mode signal upon test is a low-level fixed signal, a high-level fixed signal is input during normal operation. Further, in the case where the test mode signal upon test is a high-level fixed signal, a low-level fixed signal is input during normal operation.
Conventionally, by inputting a test mode signal to be input to each module to an OR circuit or a NAND circuit, a failure of a test mode signal (unintended test mode state) during normal operation is detected. For example, in the case where a high-level fixed signal is input to each module as a test mode signal upon implementation of the test, all the test mode signals are also input to the OR circuit. During normal operation in a normal state, because all the test mode signals become low-level fixed signals, a low-level signal is output from the OR circuit. However, in the case where an abnormality occurs in the test mode signal and at least one module to which a high-level fixed signal is input exists, a high-level signal is output from the OR circuit.
However, in such a conventional configuration, there is a problem that, in the case where the OR circuit (or the NAND circuit) itself used as a failure detection circuit fails, and, for example, a low-level fixed signal is always output regardless of a level of the input signal, even if an abnormality occurs in the test mode signal, a failure cannot be detected.